1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices (hereinafter, referred to as LSIs), and in particular relates to LSIs incorporating a block suited for a non-scan test method (hereinafter, referred to as non-scan block) and a block suited for a scan test method (hereinafter, referred to as scan block) for fault diagnosis.
2. Description of Related Art
An LSI including non-scan blocks and scan blocks has scan flip-flops (hereinafter, referred to as scan FFs) inserted at the input/output pins of the scan blocks in order to increase the fault detection rate during scan testing. FIG. 7 is a block diagram showing an example of a scan block. A scan block 60 is made of an AND circuit 61, a scan FF 62, and a NOT circuit 65. The numeral 63 denotes an input signal, 64 an output signal, 66 a scan shift-in signal, and 67 a scan shift-out signal.
FIG. 8 is a schematic view of an LSI module that includes a non-scan block and a scan block and employs a scan test method for fault diagnosis. FIG. 8A shows an LSI module 80 of the simplest conceivable configuration, and FIG. 8B shows an LSI module 90 with a configuration actually used in the prior art. The numerals 81 and 93 denote non-scan blocks, 82 and 84 denote scan FFs, and 87 denotes a selector. Numerals 85, 91 and 94 denote input signals, 86, 92 and 95 denote output signals, 88 denotes a scan shift-in signal, and 89 denotes a scan shift-out signal.
When diagnosing faults by scan testing, the Q and the DT of the scan FF are connected like a shift register. Also, in this system, the value of the scan FF is freely set by a shift in operation, the D input signal of the scan FF is taken in by a capture operation, and the scan FF value is output outside the LSI module by a shift out operation.
The non-scan blocks 81 and 93 have been designed without consideration for scan testing. For that reason, during scan testing the input signals 91 and 94 are not input to the scan FF, for example, and thus the value of the input signals 91 and 94 cannot be output outside the LSI module. Moreover, during scan testing the output signals 92 and 95 are not output to the scan FF, for example, and thus the value of the output signals 92 and 95 cannot be set.
In the case of the AND circuit 61 shown in FIG. 7, faults are detected by scan testing as described below.
First, a case where a stuck-at-0 fault on the I1 input terminal, a stuck-at-0 fault on the I2 input terminal, and a stuck-at-0 fault on the O1 output terminal of the AND circuit 61 are detected will be described. In this case, “1” must be input to the I1 input terminal and the I2 input terminal and the value of the O1 output terminal must be observed. To input “1” to the I1 input terminal it is possible to shift-in “1” to the scan FF 62. Also, to observe the value of the O1 output terminal, the scan FF 62 can be used to capture and hold the value of the O1 output terminal and then perform a shift-out operation. However, whether a “1” can be input to the I2 input terminal depends on the source supplying the input signal 63. Accordingly, conventional configurations of LSI modules also including an input stage for the AND circuit 61 are investigated below.
In the case of the LSI module 80 in FIG. 8A, the output signal 92 of the non-scan block 81 is supplied as the input signal 63, and therefore “1” cannot be intentionally input to the I2 input terminal of FIG. 7. Thus, a stuck-at-0 fault on the I1 input terminal, a stuck-at-0 fault on the I2 input terminal, and a stuck-at-0 fault on the O1 output terminal of the AND circuit 61 cannot be detected.
Consequently, in the prior art it was necessary to adopt a configuration like that of the LSI module 90 in FIG. 8B. With the LSI module 90, a selector 87 and a scan FF 82 are provided on the supply side of the input signal 63 to make it possible to set any value as the input signal 63 during scan testing using the scan FF 82. Providing the selector 87 and the scan FF 82 makes it possible intentionally to input “1” for the I2 input terminal of the AND circuit 61. Therefore, it was possible to detect a stuck-at-0 fault on the I1 input terminal, a stuck-at-0 fault on the I2 input terminal, and a stuck-at-0 fault on the O1 output terminal of the AND circuit 61.
Similarly, a predetermined value must be intentionally input to the I2 input terminal to detect a stuck-at-1 fault on the I1 input terminal or a stuck-at-1 fault on the I2 input terminal of the AND circuit 61. For that reason, a configuration such as that of the LSI module 90 of FIG. 8B was necessary.
Next, a case where a stuck-at-1 fault on the O1 output signal of the AND circuit 61 is detected will be described. In this case, a “0” must be input to either the I1 input terminal or the I2 input terminal of the AND circuit 61 and the value of the O1 output terminal must be observed. To input “0” to the I1 input terminal, it is possible to shift-in “0” to the scan FF 62. Also, to observe the value of the O1 output terminal, the scan FF 62 can capture and hold the value of the O1 output terminal and then shift-out. Controlling the scan FF 62 in this way makes it possible to detect a stuck-at-1 fault on the O1 output signal of the AND circuit 61. Consequently, a stuck-at-1 fault on the O1 output signal of the AND circuit 61 can be detected independently of whether the source supplying the input signal 63 to the scan block 60 is a signal output from a non-scan block. This means that a stuck-at-1 fault on the O1 output signal of the AND circuit 61 can be detected with either the configuration of the LSI module 80 in FIG. 8A or that of the LSI module 90 of FIG. 8B.
Faults in the NOT circuit 65 are detected by scan testing as described next.
First, a case of detecting a stuck-at-0 fault on the I3 input terminal and the O2 output terminal of the NOT circuit 65 is described. In this case, a “1” must be input to the I3 input terminal and the value of the O2 output terminal must be observed. To input “1” to the I3 input terminal, a “1” can be shifted-in to the scan FF 62. However, whether the value of the O2 output terminal can be detected depends on the supply destination of the output signal 64. Accordingly, conventional configurations of LSI modules that also include an AND circuit 61 output stage are investigated below.
In the case of the LSI module 80 shown in FIG. 8A, it is not possible to observe the value of the O2 output terminal because the output signal 64 is supplied as the input signal 94 of the non-scan block 93. Thus, a stuck-at-0 fault on the I3 input terminal and the O2 output terminal of the NOT circuit 65 cannot be detected.
On the other hand, in the case of the LSI module 90 in FIG. 8B, a further scan FF 84 has been provided as the supply destination of the output signal 64. During the scan test, the scan FF 84 is used to capture and hold the value of the output signal 64 and then shift-out so that the value of the output signal 64 can be observed outside the LSI module 90. By adopting this configuration it is possible to observe the value of the O2 output terminal and detect a stuck-at-0 fault on the I3 input terminal and the O2 output terminal of the NOT circuit 65.
Likewise, the value for the O2 output terminal also must be observed in the case of detecting a stuck-at-1 fault on the I3 input terminal and the O2 output terminal of the NOT circuit 65. Consequently, a configuration such as that of the LSI module 90 in FIG. 8B is necessary.
As explained above, the configuration of the LSI module 80 in FIG. 8A is the simplest conceivable LSI configuration, but it is not suited for scan blocks with a conventional configuration.
FIG. 9 is a collection of the conditions under which stuck-at faults on input and output terminals of the AND circuit 61 and the NOT circuit 65 of the scan block 60 can be detected. In the following explanation, the fault that is detectable when the input signal 63 can be controlled by the scan FF provided for the supply source is a fault A. The fault that is detectable when the output signal 64 can be observed with the scan FF provided for the supply source is a fault B. And a fault detectable by the scan FF 62 inside the scan block, regardless of whether the input signal 63 can be controlled by the scan FF provided for the supply source or the output signal 64 can be observed by the scan FF provided for the supply destination is expressed as a fault C.
Conventional technologies have employed a non-scan test for the analog circuit portion and a scan test for the digital circuit portion in a block including an analog circuit portion and a digital circuit portion for controlling the analog portion, such as an A/D converter (analog-digital converter). For the same reason as above, this case required the insertion of a scan FF into the path of the signal traveling between the analog circuit portion and the digital circuit portion.
FIG. 10 is a schematic view of such an A/D converter. An A/D converter 105 is made of a digital circuit portion 100, an analog circuit portion 101, scan FFs 106 and 107, and a selector 108. The numerals 102 and 103 denote input signals and 104 denotes an output signal. Like the block 60 shown in FIG. 7 that is adopted for a scan test method, there exists a fault A′ that can be detected if the signal that is input from the analog circuit portion 101 to the digital circuit portion 100 can be controlled during scan testing, and a fault B′ that can be detected if the signal that is output from the digital circuit portion 100 to the analog circuit portion 101 can be observed during scan testing. Faults A′ and B′ are detected by the scan FFs 106 and 107 and the selector 108 in the same way as described with reference to FIG. 8B.
FIG. 11 is a schematic view of a universal micro-controller LSI, which here serves as an example of an ordinary LSI. A mode control circuit 110, a ROM 111, a RAM 112, a serial I/F 113, and analog circuits 114a and 114b are the non-scan blocks. A CPU 115, a timer 116, an A/D conversion digital circuit 117, and a D/A conversion digital circuit 118 are the scan blocks. The numeral 119 denotes an input/output control circuit. Like the conventional example explained above, to increase the fault detection rate in the scan blocks during the scan test it is necessary to add a scan FF between the scan blocks and the non-scan blocks.
FIG. 12 illustrates how scan FFs and selectors for enabling scan testing are added to the universal micro-controller LSI of FIG. 11. The numerals 120 to 133 denote scan FFs and 200 to 206 denote selectors. The scan FFs 120 to 133 and the selectors 200 to 206 are inserted between scan blocks and non-scan blocks. In the case of the LSI in FIG. 12, scan FFs and selectors are inserted in seven locations.
The broken lines in FIG. 12 indicate signals that are output from the non-scan blocks. During scan testing, the value of these signals cannot be freely set. However, during scan testing, the selectors 201 to 206 switch to the output from the scan FFs 121, 123, 125, 126, 129, 131, and 133, which are capable of freely setting these values.
Also, the long-short dashed lines in FIG. 12 are signals that are input to the non-scan block. During scan testing, the value of these signals cannot be observed. However, the scan FFs 120, 122, 124, 127, 128, 130, and 132 can capture these values so that they can be observed during scan testing.
Next, the IP base design flow of the LSI will be described. FIG. 13 shows the scan circuit design flow in the IP base design of the LSI. S1 is a step for designing the scan FF block to be inserted between the non-scan block IP and the scan block IP. S2 is a step for connecting the IPs and the scan FF block. S3 is a step for verifying the connection between the IPs and the scan FF block. S4 is a step for logic synthesis of the scan FF block. S5 is a step for verifying the timing of passes where scan FFs and selectors have been inserted. S6 is a scan operation verification step.
Referencing the LSI of FIG. 12, the steps S1 to S6 will be described in more detail.
In step S1, the scan FFs 120 to 133 and the selectors 200 to 206 are designed. Normally, the scan FFs 120 to 133 and the selectors 200 to 206 are written in a RT (register transfer) level HDL (hardware descriptive language).
In step S2, the scan FFs 120 to 133, the selectors 200 to 206, the mode control circuit 110, the ROM 111, the RAM 112, the serial I/F 113, the analog circuits 114a and 114b, the CPU 115, the timer 116, the A/D conversion digital circuit 117, and the D/A conversion digital circuit 118 are connected as shown in FIG. 12.
In step S4, the RT level HDLs of the scan FFs 120 to 133 and the selectors 200 to 206 are logic synthesized and converted to a netlist.
In step S5, it is verified whether there is circuit malfunction due to line delay, which increases with the input capacity of the scan FFs 120 to 133, or signal delay, which occurs when signals pass through the selectors 200 to 206 that have been inserted.
In step S6, one chip netlist is input to an ATPG (automatic test pattern generation) tool to generate a scan pattern.
Here, scan pattern generation fails if the scan circuit has a bug, in which case the procedure returns to step S1 for designing the scan FF blocks to be inserted between the non-scan block IPs and the scan block IPs and the bug is fixed.
However, with the above conventional LSI, scan FFs and selectors must be added between the scan blocks, the CPU, the timer, the A/D conversion digital circuit, and the D/A conversion digital circuit, for example, and the non-scan blocks, the mode control circuit, the ROM, the RAM, the serial I/F, and the analog circuit, for example, during designing in order to increase the fault detection rate of the scan test. This was problematic because it lengthened the design period.
For example, the number of working days necessary for implementing the scan test with respect to the universal micro-controller LSI shown by the schematic view of FIG. 11 is as follows.
The time required for step S1 is about one day per location, so that a total of seven locations requires seven days. The time required for step S2 is about one hour per location, so that a total of seven locations requires seven hours (one day). The time required for step S3 is about one hour per location, so that a total of seven locations requires seven hours (one day). The time required for step S4 is one half day per location, so that a total of seven locations requires three and a half days. The time required for step S5 is one half day per location, so that a total of seven locations requires three and a half days. Step S6 requires one day per LSI.
Here, if there is an abnormality in the scan operation, then it is necessary to return to step S1 and redesign the LSI module. Assuming that redesigning is performed once, then the number of working days necessary to implement scan testing with respect to the universal micro-controller LSI of FIG. 11 is (7+1+1+3.5+3.5+1)×2, or in other words, 34 days.